86 search results - page 13 / 18 » A Novel Superscalar Architecture for Fast DCT Implementation |
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, we present a novel approach for parallel sorting on stream processing architectures. It is based on adaptive bitonic sorting. For sorting n values utilizing p strea...
APCSAC
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
ARC
2009
Springer
15 years 2 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
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ICDE
2004
IEEE
15 years 10 months ago
2004
IEEE
Moving objects (e.g., vehicles in road networks) continuously generate large amounts of spatio-temporal information in the form of data streams. Efficient management of such strea...