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» A Novel Superscalar Architecture for Fast DCT Implementation
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DATE
2007
IEEE
156views Hardware» more  DATE 2007»
15 years 3 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 1 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
15 years 3 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee
IEEEPACT
2006
IEEE
15 years 3 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
14 years 11 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim