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» A Parallel Evolutionary Algorithm for Circuit Partitioning
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GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
13 years 11 months ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
IPPS
2006
IEEE
14 years 8 days ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...
IPPS
2010
IEEE
13 years 3 months ago
Prototype for a large-scale static timing analyzer running on an IBM Blue Gene
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
Akintayo Holder, Christopher D. Carothers, Kerim K...
PPSN
1998
Springer
13 years 10 months ago
On Risky Methods for Local Selection under Noise
The choice of the selection method used in an evolutionary algorithm may have considerable impacts on the behavior of the entire algorithm. Therefore, earlier work was devoted to t...
Günter Rudolph
EVOW
2003
Springer
13 years 11 months ago
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages
Evolutionary Algorithms (EAs) have been proposed as a very powerful heuristic optimization technique to solve complex problems. Many case studies have shown that they work very eff...
Rolf Drechsler, Nicole Drechsler