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» A Parallel Programming Style and Its Algebra of Programs
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HIPEAC
2011
Springer
13 years 9 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
HPCA
2009
IEEE
15 years 10 months ago
Feedback mechanisms for improving probabilistic memory prefetching
This paper presents three techniques for improving the effectiveness of the recently proposed Adaptive Stream Detection (ASD) prefetching mechanism. The ASD prefetcher is a standa...
Ibrahim Hur, Calvin Lin
100
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DAMON
2007
Springer
15 years 3 months ago
Vectorized data processing on the cell broadband engine
In this work, we research the suitability of the Cell Broadband Engine for database processing. We start by outlining the main architectural features of Cell and use microbenchmar...
Sándor Héman, Niels Nes, Marcin Zuko...
HYBRID
2009
Springer
15 years 1 months ago
Trajectory Based Verification Using Local Finite-Time Invariance
Abstract. In this paper we propose a trajectory based reachability analysis by using local finite-time invariance property. Trajectory based analysis are based on the execution tra...
A. Agung Julius, George J. Pappas
TCAD
2010
121views more  TCAD 2010»
14 years 4 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta