The RACE R
parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
A new and simple network simulator Nessi is described in this paper. While other simulators focus on minimizing the simulation time, Nessi tries to minimize the development time an...
This paper presents the design and implementation of the MPI-IO interface for the Clusterfile parallel file system. The approach offers the opportunity of achieving a high corelat...
This paper presents the design of BORPH's file system layer for FPGA-based reconfigurable computers. BORPH provides user FPGA designs that execute as hardware processes acces...
This paper discusses a framework for development of bilingual and multilingual comprehension assistants and presents a prototype implementation of an English-Bulgarian comprehensi...