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» A Performance Process Maturity Model
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GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 4 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
ICDCS
2000
IEEE
15 years 4 months ago
Scheduling Heuristics for Data Requests in an Oversubscribed Network with Priorities and Deadlines
Providing up-to-date input to users’ applications is an important data management problem for a distributed computing environment, where each data storage location and intermedi...
Mitchell D. Theys, Noah Beck, Howard Jay Siegel, M...
IPPS
1998
IEEE
15 years 4 months ago
Runtime Support for Virtual BSP Computer
Abstract. Several computing environments including wide area networks and nondedicated networks of workstations are characterized by frequent unavailability of the participating ma...
Mohan V. Nibhanupudi, Boleslaw K. Szymanski
IPPS
1997
IEEE
15 years 4 months ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer
SIGMOD
1996
ACM
132views Database» more  SIGMOD 1996»
15 years 4 months ago
Cost-Based Optimization for Magic: Algebra and Implementation
Magic sets rewriting is a well-known optimization heuristic for complex decision-support queries. There can be many variants of this rewriting even for a single query, which diffe...
Praveen Seshadri, Joseph M. Hellerstein, Hamid Pir...
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