30 search results - page 4 / 6 » A Placement Methodology for Robust Clocking |
77
Voted
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The PolarBear algorithm combines recursive cutsize-dri...
92
Voted
DAC
2008
ACM
16 years 19 days ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
88
Voted
TCAD
2008
14 years 11 months ago
2008
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
105
Voted
ISQED
2010
IEEE
14 years 9 months ago
2010
IEEE
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
83
Voted
ICCAD
1999
IEEE
15 years 3 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...