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» A Placement Methodology for Robust Clocking
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ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
15 years 2 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
TMC
2010
179views more  TMC 2010»
14 years 8 months ago
On Fast and Accurate Detection of Unauthorized Wireless Access Points Using Clock Skews
We explore the use of clock skew of a wireless local area network access point (AP) as its fingerprint to detect unauthorized APs quickly and accurately. The main goal behind usi...
Suman Jana, Sneha Kumar Kasera
SAC
2005
ACM
15 years 3 months ago
Efficient placement and routing in grid-based networks
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...
Roozbeh Jafari, Foad Dabiri, Bo-Kyung Choi, Majid ...
88
Voted
DAC
2011
ACM
13 years 9 months ago
Synchronous sequential computation with molecular reactions
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
Hua Jiang, Marc D. Riedel, Keshab K. Parhi
84
Voted
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
15 years 3 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...