In this paper, we propose a run-time strategy for allocating the application tasks to platform resources in homogeneous Networks-on-Chip (NoCs). As novel contribution, we incorpor...
- This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely...
Sylvie Renaud, Jean Tomas, Yannick Bornat, Adel Da...
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
The new breed of reconfigurable integrated circuits (ICs) offer switched-capacitor based analogue circuits whose functionality can be altered during run-time. Rapidly changing th...
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...