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» A Polymorphic Hardware Platform
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ITC
2003
IEEE
124views Hardware» more  ITC 2003»
15 years 11 months ago
Power-aware NoC Reuse on the Testing of Core-based Systems
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
Érika F. Cota, Luigi Carro, Flávio R...
ASAP
2002
IEEE
76views Hardware» more  ASAP 2002»
15 years 11 months ago
A Component Architecture for FPGA-Based, DSP System Design
† Introducing FPGA components into DSP system implementations creates an assortment of challenges across system architecture and logic design. Recognizing that some of the greate...
Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakaji...
ECBS
2002
IEEE
81views Hardware» more  ECBS 2002»
15 years 11 months ago
Optimization of a Retargetable Functional Simulator for Embedded Processors
The objective of this research is to develop tools and methods for system-level optimization of embedded software that is executed on system-on-chip platforms. In particular, this...
Francesco Papariello, Gabriele Luculli
ICCAD
2002
IEEE
82views Hardware» more  ICCAD 2002»
15 years 11 months ago
Hardware/software partitioning of software binaries
Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent ...
Greg Stitt, Frank Vahid
ARC
2009
Springer
134views Hardware» more  ARC 2009»
15 years 10 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...