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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 10 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
APCSAC
2007
IEEE
15 years 10 months ago
Runtime Performance Projection Model for Dynamic Power Management
In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
Sang Jeong Lee, Hae-Kag Lee, Pen-Chung Yew
ESTIMEDIA
2007
Springer
15 years 10 months ago
Leveraging Predicated Execution for Multimedia Processing
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
Dietmar Ebner, Florian Brandner, Andreas Krall
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
15 years 10 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 10 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...