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172
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DAC
2006
ACM
16 years 7 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
174
Voted
CW
2005
IEEE
16 years 2 days ago
Designing Interfaces for art applications
Imagination and creativity have always marked the path in the world of aesthetics; artists, designers and other creative individuals have found in the realm of computers a new can...
Marissa Díaz Pier, Isaac Rudomín Gol...
ICRA
2000
IEEE
96views Robotics» more  ICRA 2000»
15 years 10 months ago
Design of Synchronized Supply Chains: A Six Sigma Tolerancing Approach
A supply chain network can be viewed as a network of facilities in which a customer order will flow through internal business processes such as procurement, production, and transp...
Y. Narahari, Nukala Viswanadham, R. Bhattacharya
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
15 years 10 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
TWC
2008
198views more  TWC 2008»
15 years 6 months ago
Cross Layer Design for Multiaccess Communication Over Rayleigh Fading Channels
Abstract-- An information theoretic queueing model is proposed in a wireless multiple access communication setup. The proposed symmetric N user model captures physical layer parame...
Vidyut Naware, Lang Tong