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» A Power-Efficient and Scalable Load-Store Queue Design
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PATMOS
2005
Springer
14 years 4 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
14 years 4 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
SAC
2008
ACM
13 years 10 months ago
Power-efficient and scalable load/store queue design via address compression
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
14 years 7 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 4 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...