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» A Predictive Performance Model for Superscalar Processors
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APCSAC
2005
IEEE
15 years 3 months ago
An Integrated Partitioning and Scheduling Based Branch Decoupling
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
Pramod Ramarao, Akhilesh Tyagi
66
Voted
HPCC
2007
Springer
15 years 3 months ago
Parallel Performance Prediction for Multigrid Codes on Distributed Memory Architectures
We propose a model for describing the parallel performance of multigrid software on distributed memory architectures. The goal of the model is to allow reliable predictions to be m...
Giuseppe Romanazzi, Peter K. Jimack
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 1 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
80
Voted
CF
2006
ACM
15 years 1 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz