225 search results - page 19 / 45 » A Predictive Performance Model for Superscalar Processors |
ANSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Statistical simulation is driven by a stream of randomly generated instructions, based on statistics collected during a single detailed simulation. This method can give accurate p...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
71
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HPCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and h...
ISPASS
2010
IEEE
15 years 4 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
107
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HPCC
2007
Springer
15 years 1 months ago
2007
Springer
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific application...