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» A Predictive Performance Model for Superscalar Processors
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IPPS
2008
IEEE
15 years 4 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
ICNS
2007
IEEE
15 years 4 months ago
A Case Study-based Performance Evaluation Framework for CSCF Processes on a Blade-Server
Abstract— The study of protocol behavior and traffic characteristics in a simulated environment is commonly supported by ad-hoc or general purpose simulators (e.g., Opnet, NS-2)...
Preetam Ghosh, Nirmalya Roy, Kalyan Basu, Sajal K....
CF
2004
ACM
15 years 3 months ago
Repairing return address stack for buffer overflow protection
Although many defense mechanisms against buffer overflow attacks have been proposed, buffer overflow vulnerability in software is still one of the most prevalent vulnerabilities e...
Yong-Joon Park, Gyungho Lee
97
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MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
14 years 7 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
DAC
2012
ACM
13 years 2 days ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra