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» A Predictive Performance Model for Superscalar Processors
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75
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ICS
2004
Tsinghua U.
15 years 3 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
EGPGV
2004
Springer
165views Visualization» more  EGPGV 2004»
15 years 3 months ago
Tuning of Algorithms for Independent Task Placement in the Context of Demand-Driven Parallel Ray Tracing
This paper investigates assignment strategies (load balancing algorithms) for process farms which solve the problem of online placement of a constant number of independent tasks w...
Tomas Plachetka
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 4 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
70
Voted
NOMS
2006
IEEE
15 years 3 months ago
Self-Adaptive SLA-Driven Capacity Management for Internet Services
— This work considers the problem of hosting multiple third-party Internet services in a cost-effective manner so as to maximize a provider’s business objective. For this purpo...
Bruno D. Abrahao, Virgilio Almeida, Jussara M. Alm...
ICS
2009
Tsinghua U.
15 years 2 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad