225 search results - page 4 / 45 » A Predictive Performance Model for Superscalar Processors |
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HPCA
2000
IEEE
15 years 2 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
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MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
MICRO
2000
IEEE
15 years 2 months ago
2000
IEEE
We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and c...
ISCA
2007
IEEE
15 years 3 months ago
2007
IEEE
Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design sp...