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» A Predictive Performance Model for Superscalar Processors
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ISHPC
1999
Springer
15 years 1 months ago
Instruction-Level Microprocessor Modeling of Scientific Applications
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
Kirk W. Cameron, Yong Luo, James Scharzmeier
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 1 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
15 years 1 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
LCPC
2004
Springer
15 years 3 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
15 years 2 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel