225 search results - page 8 / 45 » A Predictive Performance Model for Superscalar Processors |
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
In a Simultaneous Multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among ...
IEEEPACT
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...
ISPASS
2006
IEEE
15 years 3 months ago
2006
IEEE
Despite years of study, branch mispredictions remain as a significant performance impediment in pipelined superscalar processors. In general, the branch misprediction penalty can...
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
EUROPAR
2009
Springer
15 years 4 months ago
2009
Springer
While general-purpose homogeneous multi-core architectures are becoming ubiquitous, there are clear indications that, for a number of important applications, a better performance/p...