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» A Probabilistic Approach to Buffer Insertion
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ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
15 years 6 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
TCAD
2008
103views more  TCAD 2008»
15 years 1 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
SIGMOD
2009
ACM
140views Database» more  SIGMOD 2009»
15 years 8 months ago
Robust web extraction: an approach based on a probabilistic tree-edit model
On script-generated web sites, many documents share common HTML tree structure, allowing wrappers to effectively extract information of interest. Of course, the scripts and thus ...
Nilesh N. Dalvi, Philip Bohannon, Fei Sha
SIGMOD
1993
ACM
163views Database» more  SIGMOD 1993»
15 years 6 months ago
The LRU-K Page Replacement Algorithm For Database Disk Buffering
This paper introduces a new approach to database disk buffering, called the LRU–K method. The basic idea of LRU–K is to keep track of the times of the last K references to pop...
Elizabeth J. O'Neil, Patrick E. O'Neil, Gerhard We...
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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 8 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel