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MASCOTS
2003
15 years 5 months ago
Bottleneck Estimation for Load Control Gateways
Providing Quality of Service (QoS) to inelastic data transmissions in a cost-efficient, highly scalable, and realistic fashion in IP networks remains a challenging research issue....
Krishna Pandit, Jens Schmitt, Martin Karsten, Ralf...
124
Voted
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
15 years 7 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 8 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
DAC
2006
ACM
16 years 4 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
ICDCN
2010
Springer
15 years 10 months ago
Channel Assignment in Virtual Cut-through Switching Based Wireless Mesh Networks
Conventional wireless networks employ a contention based channel access mechanism, which not only imposes high latency but also reduces goodput of the network. Lack of interference...
Dola Saha, Aveek Dutta, Dirk Grunwald, Douglas C. ...