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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 8 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
BVAI
2007
Springer
15 years 7 months ago
Bounds of the Ability to Destroy Precise Coincidences by Spike Dithering
Correlation analysis of neuronal spiking activity relies on the availability of distributions for assessing significance. At present, these distributions can only be created by su...
Antonio Pazienti, Markus Diesmann, Sonja Grün
EUROCRYPT
2006
Springer
15 years 5 months ago
Learning a Parallelepiped: Cryptanalysis of GGH and NTRU Signatures
Abstract. Lattice-based signature schemes following the GoldreichGoldwasser-Halevi (GGH) design have the unusual property that each signature leaks information on the signer's...
Phong Q. Nguyen, Oded Regev
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
15 years 5 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
SCANGIS
2003
15 years 3 months ago
The Issue of Uncertainty Propagation in Spatial Decision Making
GISs give users facilities to integrate and analyze data from different sources with different scale, accuracy, resolution and quality of the original data which are the key aspect...
Rahim Ali. Abbaspour, Mahmoud Reza Delavar, Reihan...