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» A Reconfigurable Content Addressable Memory
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IPPS
2005
IEEE
15 years 3 months ago
Stream PRAM
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
Darrell R. Ulm, Michael Scherger
INFOCOM
2005
IEEE
15 years 3 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
DATE
1998
IEEE
100views Hardware» more  DATE 1998»
15 years 1 months ago
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new...
Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-J...
SC
2009
ACM
15 years 4 months ago
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such syste...
Vikas Aggarwal, Alan D. George, K. Yalamanchili, C...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
15 years 1 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan