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DSN
2007
IEEE
15 years 10 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
118
Voted
CNSR
2005
IEEE
15 years 9 months ago
Shortest-Hop Based Reliable Network Multicast
Although many multicast communication protocols have been recommended at IETF, reliable multicast communications currently rely on programs built at the application layer, e.g., m...
Ka Lun Eddie Law, Daniel Siu
135
Voted
ICDCSW
2005
IEEE
15 years 9 months ago
Forensix: A Robust, High-Performance Reconstruction System
When computer intrusions occur, one of the most costly, time-consuming, and human-intensive tasks is the analysis and recovery of the compromised system. At a time when the cost o...
Ashvin Goel, Wu-chang Feng, David Maier, Wu-chi Fe...
116
Voted
ASPLOS
2004
ACM
15 years 9 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
15 years 8 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll