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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 3 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
66
Voted
UIST
2006
ACM
15 years 3 months ago
CueTIP: a mixed-initiative interface for correcting handwriting errors
With advances in pen-based computing devices, handwriting has become an increasingly popular input modality. Researchers have put considerable effort into building intelligent rec...
Michael Shilman, Desney S. Tan, Patrice Simard
159
Voted
AAAIDEA
2005
IEEE
15 years 3 months ago
A Peer-to-Peer Infrastructure for Resilient Web Services
This paper describes an infrastructure for the deployment and use of Web Services that are resilient to the failure of the nodes that host those services. The infrastructure prese...
Stuart J. Norcross, Alan Dearle, Graham N. C. Kirb...
83
Voted
MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
15 years 3 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
ESOP
2005
Springer
15 years 3 months ago
Asserting Bytecode Safety
Abstract. We instantiate an Isabelle/HOL framework for proof carrying code to Jinja bytecode, a downsized variant of Java bytecode featuring objects, inheritance, method calls and ...
Martin Wildmoser, Tobias Nipkow