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ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
15 years 1 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
PPAM
2005
Springer
15 years 3 months ago
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
Éric Piel, Philippe Marquet, Julien Soula, ...
DSN
2007
IEEE
15 years 4 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
IPPS
2003
IEEE
15 years 3 months ago
Flexible CoScheduling: Mitigating Load Imbalance and Improving Utilization of Heterogeneous Resources
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
Eitan Frachtenberg, Dror G. Feitelson, Fabrizio Pe...
HPCA
2000
IEEE
15 years 2 months ago
Software-Controlled Multithreading Using Informing Memory Operations
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
Todd C. Mowry, Sherwyn R. Ramkissoon