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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 2 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
SOSP
1993
ACM
14 years 11 months ago
Improving IPC by Kernel Design
Inter-process communication (ipc) has to be fast and e ective, otherwise programmers will not use remote procedure calls(RPC),multithreadingand multitasking adequately. Thus ipc p...
Jochen Liedtke
PLDI
1994
ACM
15 years 1 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
72
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IPPS
2005
IEEE
15 years 3 months ago
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
Robert L. McGregor, Christos D. Antonopoulos, Dimi...
VLDB
1999
ACM
145views Database» more  VLDB 1999»
15 years 1 months ago
DBMSs on a Modern Processor: Where Does Time Go?
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...