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NCA
2006
IEEE
14 years 9 months ago
Evolutionary training of hardware realizable multilayer perceptrons
The use of multilayer perceptrons (MLP) with threshold functions (binary step function activations) greatly reduces the complexity of the hardware implementation of neural networks...
Vassilis P. Plagianakos, George D. Magoulas, Micha...
FPL
2006
Springer
125views Hardware» more  FPL 2006»
15 years 1 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt
AUSDM
2008
Springer
238views Data Mining» more  AUSDM 2008»
14 years 11 months ago
Graphics Hardware based Efficient and Scalable Fuzzy C-Means Clustering
The exceptional growth of graphics hardware in programmability and data processing speed in the past few years has fuelled extensive research in using it for general purpose compu...
S. A. Arul Shalom, Manoranjan Dash, Minh Tue
IPPS
2005
IEEE
15 years 3 months ago
A Hardware Acceleration Unit for MPI Queue Processing
With the heavy reliance of modern scientific applications upon the MPI Standard, it has become critical for the implementation of MPI to be as capable and as fast as possible. Th...
Keith D. Underwood, K. Scott Hemmert, Arun Rodrigu...
ISPASS
2010
IEEE
15 years 4 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...