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IOPADS
1996
100views more  IOPADS 1996»
14 years 11 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
HPCA
2009
IEEE
15 years 10 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 8 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
IPPS
1999
IEEE
15 years 2 months ago
Distributed, Scalable, Dependable Real-Time Systems: Middleware Services and Applications
Some classes of real-time systems function in environments which cannot be modeled with static approaches. In such environments, the arrival rates of events which drive transient ...
Lonnie R. Welch, Binoy Ravindran, Paul V. Werme, M...
FCCM
2007
IEEE
117views VLSI» more  FCCM 2007»
15 years 4 months ago
FPGA Acceleration of Gene Rearrangement Analysis
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
Jason D. Bakos