Sciweavers

983 search results - page 83 / 197
» A Region-Oriented Hardware Implementation for Membrane Compu...
Sort
View
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
15 years 4 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 4 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
ERSA
2010
172views Hardware» more  ERSA 2010»
14 years 8 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
ICA3PP
2005
Springer
15 years 3 months ago
A Low-Level Communication Library for Java HPC
Abstract. Designing a simple but powerful low-level communication library for Java HPC environments is an important task. We introduce new low-level communication library for Java ...
Sang Boem Lim, Bryan Carpenter, Geoffrey Fox, Han-...
FPL
2003
Springer
146views Hardware» more  FPL 2003»
15 years 3 months ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall