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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
15 years 4 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
15 years 3 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
CAV
2009
Springer
133views Hardware» more  CAV 2009»
15 years 10 months ago
Cardinality Abstraction for Declarative Networking Applications
ity Abstraction for Declarative Networking Applications Juan A. Navarro P?erez, Andrey Rybalchenko, and Atul Singh Max Planck Institute for Software Systems (MPI-SWS) Declarative N...
Andrey Rybalchenko, Atul Singh, Juan Antonio Navar...
CODES
2009
IEEE
15 years 1 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
FPL
1999
Springer
95views Hardware» more  FPL 1999»
15 years 2 months ago
FPGA Viruses
Programmable logic is widely used, for applications ranging from eld-upgradable subsystems to advanced uses such as recon gurable computing platforms which are modi able at run-tim...
Ilija Hadzic, Sanjay Udani, Jonathan M. Smith