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DANCE
2002
IEEE
15 years 2 months ago
Design and Evaluation of a High Performance Dynamically Extensible Router
This paper describes the design, implementation and performance of an open, high performance, dynamically extensible router under development at Washington University in St. Louis...
Fred Kuhns, John D. DeHart, Anshul Kantawala, Ralp...
FPL
2008
Springer
154views Hardware» more  FPL 2008»
14 years 11 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
VC
2008
138views more  VC 2008»
14 years 9 months ago
A GPU-based light hierarchy for real-time approximate illumination
Illumination rendering including environment lighting, indirect illumination, and subsurface scattering plays for many graphics applications such as games and VR systems. However, ...
Hyunwoo Ki, Kyoungsu Oh
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
15 years 4 months ago
A memory optimization technique for software-managed scratchpad memory in GPUs
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
15 years 6 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif