27 search results - page 5 / 6 » A Robust Parallel Delta-Sigma A D Converter Architecture |
ICPP
2003
IEEE
15 years 3 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
MIDDLEWARE
2005
Springer
15 years 3 months ago
2005
Springer
Advances in MEMS technology, wireless communications, and digital electronics have enabled the development of low-cost, low-power, multifunctional sensor nodes that integrating th...
HPCA
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
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WACV
2005
IEEE
15 years 3 months ago
2005
IEEE
Many existing systems for human body tracking are based on dynamic model-based tracking that is driven by local image features. Alternatively, within a view-based approach, tracki...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...