Sciweavers

34 search results - page 6 / 7
» A SIMD Vectorizing Compiler for Digital Signal Processing Al...
Sort
View
ICFP
2012
ACM
11 years 8 months ago
Nested data-parallelism on the gpu
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
Lars Bergstrom, John H. Reppy
CASES
2010
ACM
13 years 4 months ago
Resource recycling: putting idle resources to work on a composable accelerator
Mobile computing platforms in the form of smart phones, netbooks, and personal digital assistants have become an integral part of our everyday lives. Moving ahead to the future, m...
Yongjun Park, Hyunchul Park, Scott A. Mahlke, Sukj...
CODES
2005
IEEE
13 years 12 months ago
Future wireless convergence platforms
As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, suppor...
C. John Glossner, Mayan Moudgill, Daniel Iancu, Ga...
VLSISP
2008
100views more  VLSISP 2008»
13 years 6 months ago
Memory-constrained Block Processing for DSP Software Optimization
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...
ICASSP
2011
IEEE
12 years 10 months ago
Rapid feature space MLLR speaker adaptation with bilinear models
In this paper, we propose a novel method for rapid feature space Maximum Likelihood Linear Regression (FMLLR) speaker adaptation based on bilinear models. When the amount of adapt...
Shilei Zhang, Peder A. Olsen, Yong Qin