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» A Scalable Architecture for Maximizing Concurrency
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Publication
248views
14 years 8 months ago
Equalizer: A Scalable Parallel Rendering Framework
Continuing improvements in CPU and GPU performances as well as increasing multi-core processor and cluster-based parallelism demand for flexible and scalable parallel rendering sol...
Stefan Eilemann, Maxim Makhinya, Renato Pajarola
PLDI
2012
ACM
13 years 2 months ago
Dynamic synthesis for relaxed memory models
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
Feng Liu, Nayden Nedev, Nedyalko Prisadnikov, Mart...
AGENTS
2000
Springer
15 years 4 months ago
Tools for Developing and Monitoring Agents in Distributed Multi-Agent Systems
Before the powerful agent programming paradigm can be adopted in commercial or industrial settings, a complete environment, similar to that for other programming languages, must b...
John R. Graham, Daniel McHugh, Michael Mersic, Fos...
SDL
2003
147views Hardware» more  SDL 2003»
15 years 1 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
BWCCA
2010
14 years 6 months ago
Advanced Design Issues for OASIS Network-on-Chip Architecture
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, K...