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FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 3 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
USITS
2003
14 years 11 months ago
Using Random Subsets to Build Scalable Network Services
In this paper, we argue that a broad range of large-scale network services would benefit from a scalable mechanism for delivering state about a random subset of global participan...
Dejan Kostic, Adolfo Rodriguez, Jeannie R. Albrech...
ICC
2007
IEEE
138views Communications» more  ICC 2007»
15 years 4 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
ICIAR
2005
Springer
15 years 3 months ago
Scalable e-Learning Multimedia Adaptation Architecture
A neglected challenge in existing e-Learning (eL) systems is providing access to multimedia to all users regardless of environmental conditions such as diverse device capabilities,...
Mazen Almaoui, Konstantinos N. Plataniotis
WMPI
2004
ACM
15 years 3 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar