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ASPLOS
2010
ACM
15 years 10 months ago
Analyzing multicore dumps to facilitate concurrency bug reproduction
Debugging concurrent programs is difficult. This is primarily because the inherent non-determinism that arises because of scheduler interleavings makes it hard to easily reproduc...
Dasarath Weeratunge, Xiangyu Zhang, Suresh Jaganna...
ASWEC
2009
IEEE
15 years 1 months ago
From Requirements to Embedded Software - Formalising the Key Steps
Failure of a design to satisfy a system's requirements can result in schedule and cost overruns. When using current approaches, ensuring requirements are satisfied is often d...
Toby Myers, R. Geoff Dromey
ECRTS
2002
IEEE
15 years 8 months ago
Weakly Hard Real-time Constraints on Controller Area Network
For priority based buses such as CAN, worst case response time analysis is able to determine whether messages always meet their deadlines. This can include system models with boun...
Ian Broster, Guillem Bernat, Alan Burns
124
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RTSS
1998
IEEE
15 years 7 months ago
Statistical Delay Guarantee of Virtual Clock
In this paper, we derive a statistical delay guarantee of the generalized Virtual Clock scheduling algorithm. We define the concept of an equivalent fluid and packet source and pr...
Pawan Goyal, Harrick M. Vin
TC
2008
15 years 3 months ago
Minimum Deadline Calculation for Periodic Real-Time Tasks in Dynamic Priority Systems
Real-time systems are often designed using a set of periodic tasks. Task periods are usually set by the system requirements, but deadlines and computation times can be modified in ...
Patricia Balbastre, Ismael Ripoll, Alfons Crespo