Sciweavers

109 search results - page 11 / 22
» A Self-Tuning Cache Architecture for Embedded Systems
Sort
View
93
Voted
DATE
2002
IEEE
104views Hardware» more  DATE 2002»
15 years 4 months ago
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
Luca Benini, Davide Bruni, Alberto Macii, Enrico M...
93
Voted
ISORC
2009
IEEE
15 years 6 months ago
Thread-Local Scope Caching for Real-time Java
There is increasing convergence between the fields of parallel and embedded computing. The demand for more functionality in embedded devices means that complex multicore architec...
Andy J. Wellings, Martin Schoeberl
RTAS
2005
IEEE
15 years 5 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
DAC
2008
ACM
16 years 20 days ago
Cache modeling in probabilistic execution time analysis
Multimedia-dominated consumer electronics devices (such as cellular phone, digital camera, etc.) operate under soft real-time constraints. Overly pessimistic worst-case execution ...
Yun Liang, Tulika Mitra
ECRTS
2005
IEEE
15 years 5 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...