109 search results - page 13 / 22 » A Self-Tuning Cache Architecture for Embedded Systems |
103
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SAMOS
2007
Springer
15 years 5 months ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
ISLPED
2003
ACM
15 years 4 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
SBACPAD
2009
IEEE
15 years 6 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
162
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DATE
2011
IEEE
14 years 3 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
DAC
2004
ACM
16 years 19 days ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...