109 search results - page 17 / 22 » A Self-Tuning Cache Architecture for Embedded Systems |
160
Voted
DAC
2009
ACM
16 years 6 months ago
2009
ACM
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
167
Voted
NOCS
2007
IEEE
15 years 11 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
166
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ISCA
2003
IEEE
15 years 10 months ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
135
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FCCM
2006
IEEE
15 years 11 months ago
2006
IEEE
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
169
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WMPI
2004
ACM
15 years 10 months ago
2004
ACM
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...