109 search results - page 3 / 22 » A Self-Tuning Cache Architecture for Embedded Systems |
139
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CASES
2008
ACM
15 years 7 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
113
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ISCA
2003
IEEE
15 years 10 months ago
2003
IEEE
156
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DATE
1999
IEEE
15 years 9 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
134
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ICCAD
2002
IEEE
16 years 1 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
147
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DAC
2008
ACM
16 years 6 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...