109 search results - page 8 / 22 » A Self-Tuning Cache Architecture for Embedded Systems |
ICS
2005
Tsinghua U.
15 years 5 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...
114
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DAC
2010
ACM
14 years 12 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
107
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GLVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...