109 search results - page 9 / 22 » A Self-Tuning Cache Architecture for Embedded Systems |
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
126
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JTRES
2010
ACM
14 years 12 months ago
2010
ACM
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
114
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GLVLSI
2010
IEEE
15 years 1 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
110
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ECRTS
2008
IEEE
15 years 6 months ago
2008
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...