Sciweavers

132 search results - page 10 / 27
» A Self-Tuning Configurable Cache
Sort
View
DAC
2009
ACM
16 years 20 days ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
79
Voted
USENIX
1996
15 years 29 days ago
A Hierarchical Internet Object Cache
: This paper discussesthedesignandperformance of a hierarchical proxy-cache designed to make Internet information systems scale better. The design was motivated by our earlier trac...
Anawat Chankhunthod, Peter B. Danzig, Chuck Neerda...
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 3 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
84
Voted
WWW
2001
ACM
16 years 9 days ago
Integrating Software Agents into the HTTP Caching Infrastructure
Mobile software agents are an increasingly important programming model within the World Wide Web (WWW). Typically programmed in Java or another machine- independent language, the ...
Jesse Greenwald, Daniel Andresen
IPPS
2006
IEEE
15 years 5 months ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...