Sciweavers

132 search results - page 4 / 27
» A Self-Tuning Configurable Cache
Sort
View
87
Voted
APCSAC
2001
IEEE
15 years 3 months ago
Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
Rajiv A. Ravindran, Rajat Moona
96
Voted
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
15 years 4 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid
CODES
2005
IEEE
15 years 1 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
FPGA
1999
ACM
144views FPGA» more  FPGA 1999»
15 years 3 months ago
Configuration Caching Vs Data Caching for Striped FPGAs
Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
109
Voted
GLOBECOM
2010
IEEE
14 years 9 months ago
Cache-Based Scalable Deep Packet Inspection with Predictive Automaton
Abstract--Regular expression (Regex) becomes the standard signature language for security and application detection. Deterministic finite automata (DFAs) are widely used to perform...
Yi Tang, Junchen Jiang, Xiaofei Wang, Yi Wang, Bin...