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» A Sequential Reduction Strategy
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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 2 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
FOSSACS
2001
Springer
15 years 2 months ago
On Regular Message Sequence Chart Languages and Relationships to Mazurkiewicz Trace Theory
Hierarchical Message Sequence Charts are a well-established formalism to specify telecommunication protocols. In this model, numerous undecidability results were obtained recently ...
Rémi Morin
ICCAD
2000
IEEE
119views Hardware» more  ICCAD 2000»
15 years 2 months ago
Synthesis of Operation-Centric Hardware Descriptions
Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer ...
James C. Hoe, Arvind
SPAA
1997
ACM
15 years 1 months ago
A Localized Algorithm for Parallel Association Mining
Discovery of association rules is an important database mining problem. Mining for association rules involves extracting patterns from large databases and inferring useful rules f...
Mohammed Javeed Zaki, Srinivasan Parthasarathy, We...
DATE
2010
IEEE
195views Hardware» more  DATE 2010»
15 years 4 days ago
Cool MPSoC programming
Abstract--This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key driver...
Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart ...