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IPPS
2008
IEEE
15 years 4 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
15 years 2 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
AAAI
2008
15 years 7 days ago
Adapting ADtrees for High Arity Features
ADtrees, a data structure useful for caching sufficient statistics, have been successfully adapted to grow lazily when memory is limited and to update sequentially with an increme...
Robert Van Dam, Irene Langkilde-Geary, Dan Ventura
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
14 years 11 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
TCAD
1998
91views more  TCAD 1998»
14 years 9 months ago
Cost-free scan: a low-overhead scan path design
Conventional scan design imposes considerable area and delay overhead by using larger scan ip- ops and additional scan wires without utilizing the functionality of the combinatio...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Ti...