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FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 1 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
UAI
2008
15 years 1 months ago
Learning Inclusion-Optimal Chordal Graphs
Chordal graphs can be used to encode dependency models that are representable by both directed acyclic and undirected graphs. This paper discusses a very simple and efficient algo...
Vincent Auvray, Louis Wehenkel
RSS
2007
147views Robotics» more  RSS 2007»
15 years 1 months ago
Composition of Vector Fields for Multi-Robot Manipulation via Caging
Abstract— This paper describes a novel approach for multirobot caging and manipulation, which relies on the team of robots forming patterns that trap the object to be manipulated...
Jonathan Fink, Nathan Michael, Vijay Kumar
CATA
2006
15 years 1 months ago
Understanding the Behavior of Simultaneous Multithreaded and Multiprocessor Architectures
Neither simulation results nor real system results give an explanation to the behavior of advanced computer systems for the full design spectrum. In this paper, we present simple ...
Nagi N. Mekhiel
ESANN
1997
15 years 1 months ago
Kohonen maps versus vector quantization for data analysis
Besides their topological properties, Kohonen maps are often used for vector quantization only. These auto-organised networks are often compared to other standard and/or adaptive v...
Eric de Bodt, Michel Verleysen, Marie Cottrell