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ITC
2000
IEEE
68views Hardware» more  ITC 2000»
15 years 2 months ago
Current ratios: a self-scaling technique for production IDDQ testing
The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describ...
Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, ...
IPPS
1998
IEEE
15 years 2 months ago
Capturing the Connectivity of High-Dimensional Geometric Spaces by Parallelizable Random Sampling Techniques
Abstract. Finding paths in high-dimensional gemetric spaces is a provably hard problem. Recently, a general randomized planning scheme has emerged as an e ective approach to solve ...
David Hsu, Lydia E. Kavraki, Jean-Claude Latombe, ...
SC
1993
ACM
15 years 1 months ago
Runtime compilation techniques for data partitioning and communication schedule reuse
In this paper, we describe two new ideas by which HPF compiler can deal with irregular computations e ectively. The rst mechanism invokes a user speci ed mapping procedure via a s...
Ravi Ponnusamy, Joel H. Saltz, Alok N. Choudhary
DAC
1994
ACM
15 years 1 months ago
New Techniques for Efficient Verification with Implicitly Conjoined BDDs
-- In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to addres...
Alan J. Hu, Gary York, David L. Dill
EUC
2008
Springer
14 years 11 months ago
Performance Comparison of Techniques on Static Path Analysis of WCET
Static path analysis is a key process of Worst Case Execution Time (WCET) estimation, the objective of which is to find the execution path that has the largest execution time. Cur...
Mingsong Lv, Zonghua Gu, Nan Guan, Qingxu Deng, Ge...